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ABSTRACT:
The integration of complete Network-on-chip (NoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. But, the communication between the IP Cores is the main issue in recent years. This paper presents an On-Chip interconnect mechanism as a component of Code Division Multiple Access (CDMA) for shared bus architecture to communicate between IP cores in SoC. In the proposal, only bus lines that carry address and data signals are CDMA coded. CDMA technology has better channel isolation, channel continuity, data integrity and also reduces the number of lines in the shared bus for transmitting the data from master to slave
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